Field
Aspects of the present innovations relate to or involve phase frequency detection including features such as clock reset, extended detection range, reduction of reverse charge after cycle slipping and/or other features.
Description of Related Information
Phase-Locked Loop (PLL) is a popular circuit for locking an output clock and a reference clock in phase and frequency. For example, PLL circuitry may be used to generate an output clock with clock edge aligned to reference clock at a specific frequency ratio to the reference clock. FIG. 1 shows a typical PLL block diagram. Such PLL circuitry uses the phase-frequency-detector (PFD) 102 to detect the frequency and phase difference and a charge pump (CP) 104 for adjusting input voltage of voltage-controlled oscillator (VCO) 106 and then changing the output frequency and phase of the VCO accordingly.
FIG. 2 shows a conventional design with a PFD circuit 102 and a Charge-Pump (CP) circuit 104 connected. The PFD generates two output signals including an up pulse 202, i.e., “up” to charge up the CP output, and a down pulse 204, i.e., “dn” to discharge the CP output, in proportion to the phase difference between the reference input clock 206 (e.g. clock_ref) and the VCO output clock 208 (e.g. clock_fb). The PLL uses these “up” and “dn” output signals to lock in the phase of the reference clock and the VCO feedback clock. When there is a frequency difference between the reference clock and the VCO feedback clock, the CP output controlled by the PFD has a DC component to pull in the frequency of VCO clock for matching the frequency of reference clock.
FIG. 3 shows an ideal transfer curve of the PFD along with real transfer curves after considering the non-ideal effects in the real implementation. Non-ideal effects of a conventional implementation are shown in FIG. 4. One non-ideal effect shown on the curves of FIGS. 3 and 4 relates to a required minimum width 302, which is necessary to avoid a dead-zone. Another non-ideal effect shown in FIG. 3, at 304, includes both the minimum width 302 and a wasted time period 306, which is generated due to the round trip of “rstb” and shown by itself in FIG. 4. Non-ideal effects also include cycle slipping where, by nature, with two input clocks in different frequency, there must be cycle slipping at a certain point to re-choose clock edge for comparison. Furthermore, after cycle slipping, the output of PFD+CP can be reversed.